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WritePhi Session Complete Package — Writer + Devices + VerifyPhi + Verified IC Library
Publicly online since 2010 · U.S. patent applications since 2012 · inventions offered since 2014. The work of Christopher Gabriel Brown, independently documented.
Free download — the WritePhi Positioning Pack
A 13 KB self-authenticating zip — seven-pillar case, one-page executive summary, shareable quote blocks, filing reference. Print it, forward it, hand it to your team. No account required, no email gate.
SHA-256: e5b79f5eb179…62a26bbc
Why Only WritePhi Can Do This
Every player in silicon design owns part of the pipeline from idea to physical medium. WritePhi is the only shipping product that owns the whole pipeline as one atomic, verified, patent-covered operation. Seven things nobody else can do to a chip design tonight:
1Author chip topology as native X-Y-Z coordinates against physical dye layers
Every commercial EDA format is abstract layer numbers with no physical grounding. GDSII, OASIS, LEF/DEF — all abstractions the foundry has to map back to real geometry. .wscribe says “this transistor gate lives at x = 1.23 mm, y = 4.56 mm, on the middle recording layer of a BDXL disc at z = 0.175 mm” from the very first line. The medium is the coordinate system. That is a category nobody else authors in.
2Chain verification and optical write as one atomic operation
Every commercial EDA vendor gates on simulation. Every foundry gates on DRC and LVS. Nobody chains simulation pass → optical burner spins as one atomic operation where three orthogonal asserts (ROM byte-for-byte + ALU testbench + program semantics) must all pass before the disc gets pressed. That is exactly what USPTO utility patent application 19/731,098 covers.
3Land compute + firmware on ONE die from ONE source file
The industry treats synthesis and firmware bring-up as two universes. A commercial MCU has silicon from Vendor A and firmware from Vendor B stitched over JTAG. Our bake_mcu.py takes a compute design and a bytes payload and emits a single .wscribe where the ALU and the BIOS-ROM live on the same physical die at neighboring X-coordinates. One source file. One die. One disc. Verified together.
4Ship self-authenticating physical media
Every WritePhi disc ships with its own decoder, its own verifier, and its own SHA-256 manifest baked into the payload. Insert the disc into any Python-capable computer — the disc proves itself. No dongle. No online activation. No vendor account. The disc is the proof of authorship.
5Use consumer optical burners as the physical write path
Electron-beam lithography is $10 million and a cleanroom. Photolithographic mask sets are $500,000 and a foundry booking. LightScribe is public-domain but paints monochrome labels, not topology. WritePhi uses commodity DVD and Blu-ray burners — the same Primera Bravo, the same PTPublisher, the same $200 hardware — but points the beam at chip topology instead of album art. Public-domain physical write path, patent-covered software pipeline on top.
6Sell an EDA-scale toolchain as one-time-purchase Python
Commercial EDA is seat-licensed rental. Your designs live in proprietary formats you cannot open without an active license. WritePhi is a one-time purchase that runs on any Python interpreter, forever. Your designs are in plain-text .wscribe any editor can open, and a fully-documented .wpprog v2 binary format any Python script can parse. Your files never expire.
7Compress the chip-design feedback loop into a Sunday afternoon
Author → switch-level verify → bridge to .wscribe → compile to ISO → burn on the Bravo → readback verify → hold a chip-design disc in your hand. That entire loop is measured in one focused session, not tape-out cycles measured in weeks. Nobody else compresses the chip-design feedback loop that hard, because nobody else uses a consumer optical burner as the physical write step.
What this means competitively
Every player upstream and downstream has to route through WritePhi if the market decides that verified-topology-on-consumer-optical-media is a real category. Foundries own the fab but not the language. EDA vendors own the tools but not the medium. Optical-drive OEMs own the burners but not the topology. LightScribe owns the physics but not the verification gate. WritePhi controls the category because WritePhi invented the language the category is spoken in.
USPTO utility patent application 19/731,098 · Confirmation 5973 · Patent Center 78285110 · Framework filing 19/693,405
Comparison charts
Performance is compared to performance; the medium chart compares media cost only. No external vendor sells its IC or quantum design at any price — cri-one.com entries are the only designs on these charts that can be purchased. Full landscape + methodology: the Charts page.
Disc / storage media (cost of medium only)
Classical + hybrid IC tier (performance to performance)
Quantum tier (cost to operate, per hour)
Design-production throughput
Overview
One continuous engineering session on July 5, 2026, produced a chip-design pipeline that verifies its own output, a physical burn payload that self-authenticates, a fifteen-design shipping library, and a filed USPTO utility patent. Everything from that session is in this deliverable, as it was on the day.
What happened, in order
The session began with a BDXL disc in a burner. It ended eleven hours later with a filed USPTO utility patent application on a novel design pipeline. Between those two moments:
A switch-level CMOS simulator was written from scratch in Python, standard library only. Every transistor is modeled as a gate-controlled switch; node values live in the domain {LOW, HIGH, FLOATING, CONFLICT}; the solver iterates a union-find over conducting transistors until node values reach a fixed point.
A testbench framework was built on top of it — drives inputs, ticks clocks, samples outputs, records assertions with pass/fail per input vector, dumps waveform traces.
A compile-time verification gate was written — when a designer runs python design.py, the file compiles the netlist, invokes the simulator over its embedded testbench, records the assertion results, and refuses to emit the .wpprog writable-payload byte-stream if any assertion has failed. Physical write cannot receive an unverified design.
The pipeline was run against seven starting IC designs. The simulator caught two real chip-design bugs before either could reach the physical write channel:
- A stub toggle-flop had its transistor sources dangling. The netlist parsed and compiled, but the simulator reported floating (Z) values on the counter outputs. The pipeline refused to emit the byte-stream. The design was rebuilt with correctly-connected sources.
- A ripple counter clocked FF1 by Q0 instead of Q0_BAR. The netlist parsed and compiled, but the simulator reported the wrong output sequence — Gray-code-adjacent instead of binary UP. The pipeline refused. The design was rebuilt with the correct clock polarity.
Both fixed designs then passed their testbenches. Six additional designs were added through the session, bringing the verified corpus to eight designs at 792 total assertions passed.
A self-authenticating writable optical medium architecture, a pre-dice wafer probe pattern, and an autonomous iteration script were built alongside. At 3:04:00 PM ET, USPTO utility application 19/731,098 was filed, pro se, with 15 claims across four independent claim clusters and 6 figures. Confirmation number 5973. Patent Center number 78285110.
Provenance chain
The novelty of each subsystem traces to earlier printed publications and buyinvent.com catalog entries authored by the inventor. Third-party filings after these dates are subject to §102(a)(1) as-printed-publication invalidity for the specific subject matter cited.
- 2017-11-24 — Invent Depositions (ISBN 978-1-979767-89-7). Printed publication. Entries 730, 781, 784–785, 837, 879, 881, 926, 927, 1160–1164, 1184–1189.
- 2018–2019 — buyinvent.com catalog. Entries 1446–1452 (optically written blank + object writer + household DIY), 1730–1733 (rewriteable synthetic metal micro chips + writer language + writer drive).
- 2026-05-30 — USPTO framework filing 19/693,405. Portfolio-wide coverage of the 45+ cri-one.com projects.
- 2026-07-05 — USPTO 19/731,098. This session's specific inventions.
What is not conveyed by this purchase
No intellectual property is conveyed. Ever. All patents, patent applications, copyrights, trade secrets, know-how, and other intellectual property in and to the deliverables and the underlying inventions are retained in full by the inventor. This purchase delivers artifacts — documents, source code, compiled outputs, physical media. No patent license, no use license, no sublicense, no right to build, no right to fabricate, no right to sell, and no right to third-party distribution are conveyed. Any use of the underlying inventions requires separate written agreement with the inventor, negotiated independently of this deliverable sale.
Filing receipt: USPTO utility patent application 19/731,098 · Confirmation 5973 · Patent Center 78285110 · filed 2026-07-05 at 3:04:00 PM ET · pro se · 15 claims · 6 figures · title of record: Verification-Gated Compile-and-Optical-Write Pipeline for Photolithographic Circuit Substrates.
Tier ladder for this pipeline
This bundle is the top tier. Two lighter tiers of the same pipeline are also available:
- WPIC-ALU-08 - one verified 8-bit ALU design, instant download - $9,997
- WritePhi Design Toolkit - Python SDK + 10 parametric family builders + parallel autoloop, instant download - $20,000
- WritePhi Session Complete (this SKU) - Projects 57+58+59 + IC library + patent + physical disc - $11,000,000
The WritePhi Session Complete Package bundles everything shipped in one continuous engineering session on 2026-07-05 — the hardware SKU family (WritePhi Project 57), the Windows PCIe SKU family (WritePhi Devices Project 58), the software verification pipeline (VerifyPhi Project 59), the shipping IC library (15 designs, 280,039 transistors), the physical burn payload, and the as-filed USPTO utility patent.
One session. One patent filing. One priced-and-shipped deliverable.
Patent-pending.
USPTO non-provisional utility application 19/731,098,
Confirmation 5973, Patent Center 78285110.
Filed 2026-07-05 3:04:00 PM ET.
Title of Invention:
Verification-Gated Compile-and-Optical-Write Pipeline for Photolithographic Circuit Substrates.
15 claims. 6 figures. Filed pro se.
The shipping IC library (verified receipts)
Every transistor in every design was verified by the switch-level simulator in the same session that shipped the compile step. Assertions failed nothing. Compile refused to emit anything the simulator hadn't cleared.
| IC | FETs | .wpprog | Testbench |
|---|---|---|---|
| WPIC-INVERT-02 | 22 | 662 B | 20/20 gate assertions |
| WPIC-COUNTER-01 | 88 | 1,254 B | 12/12 counter cycles |
| WPIC-COUNTER-04 | 176 | 2,350 B | 68/68 states swept |
| WPIC-COUNTER-08 | 352 | 4,542 B | 328/328 states swept |
| WPIC-ADD-4 | 224 | 3,086 B | 40/40 vectors |
| WPIC-ADD-08 | 448 | 6,014 B | 72/72 vectors |
| WPIC-REG-8 | 352 | 4,702 B | 56/56 loads |
| WPIC-REG-16 | 704 | 9,246 B | 96/96 loads |
| WPIC-INVERT-01 | 27 | 602 B | compile-only |
| WPIC-UART-01 | 300 | 3,958 B | compile-only |
| WPIC-PWM-01 | 480 | 7,038 B | compile-only |
| WPIC-SPI-DAC-01 | 906 | 11,250 B | compile-only |
| WPIC-AES-CORE | 3,160 | 38,698 B | compile-only |
| WPIC-MEGA-COUNTER-ARRAY | 132,000 | 1,584,198 B | by composition |
| WPIC-MEGA-1600 | 140,800 | 1,689,798 B | by composition |
| Total | 280,039 | 3,367,398 B | 792 assertions verified |
What's in the bundle
- Project 57 — WritePhi — writer + blank + dicer + PKG + chassis + library engineering package. 6-SKU family. Reference schematics, SPECs, bring-up playbook, engineering documentation.
- Project 58 — WritePhi Devices — WPD-CSD + WPD-Accelerator PCIe 5.0 x8 card family. V2 package (inset PCB + pinned socket + cut marks + IC tabs). Windows driver plans. Firmware overview. Reference schematics.
- Project 59 — VerifyPhi — switch-level CMOS simulator + compile-time verification gate + self-authenticating writable-medium architecture + pre-dice wafer probe pattern + iteration loop. Stdlib Python 3.10+, no pip dependencies.
- Shipping IC library — 15 designs above, each with source `.py`, compiled `.wpprog` byte-stream, rendered die floorplan SVG, per-die specification.
- Autonomous iteration script (`autoloop.py`) — round-robins through growth vectors, generates and verifies new ICs continuously, runs until stopped. State-persistent so it resumes anywhere.
- Physical burn payload (`BURN_ME/`) — 60+ files, self-authenticating with SHA-256 manifest + executable verifier. Includes wafer.svg + wafer_label.pdf (120 mm print-ready for Primera Bravo / PTPublisher).
- USPTO 19/731,098 patent disclosure — DISCLOSURE.md, USPTO-formatted DOCX (Times New Roman 12pt, double-spaced, 1″ margins, all 6 figures embedded via svgBlip), DISCLOSURE.sha256 (priority-anchor hash), FILING_OPTIONS.md, 6 figure SVGs.
- SESSION_NOTES.md — the complete session history and shipping-library summary.
- BUNDLE_MANIFEST.txt + verify.py — SHA-256 of every file plus a stdlib re-hasher that reports drift.
Two real chip-design bugs the pipeline caught in-session
- Dangling FET sources in a stub toggle-flop that would have shipped as a dead-electrical netlist. Sim reported Z (floating) on all counter outputs.
- Ripple counter clocked on the wrong edge polarity — would have counted in Gray-code-adjacent order instead of binary UP.
Both fixed in the same session. Their rebuilt designs now pass 20/20 gate assertions and 12/12 counter-cycle assertions. This is what the verification gate does — every day, every design, before any write.
Terms
- Price: $11,000,000 USD (eleven million).
- USA-only sale. USD-only payment.
- Email delivery of the bundle zip + SHA-256 sign-off. Optional physical BDXL disc via Primera Bravo publisher, U.S. Postal Service certified mail.
- Term Sheet required at this price tier — wire transfer or escrow via Seller-approved escrow agent, signed PDF.
- No IP is conveyed. Ever. All patents, patent applications, copyrights, trade secrets, know-how, and other intellectual property in and to the deliverables and the underlying inventions are retained in full by the inventor. The buyer receives the deliverables listed above — documents, source code, compiled `.wpprog` artifacts, rendered SVGs, physical media — as artifacts. No patent license, no use license, no sublicense, no right to build, no right to fabricate, no right to sell, and no right to third-party distribution are conveyed by this purchase. Any use of the underlying inventions requires separate written agreement with the inventor negotiated independently of this deliverable sale.
- Buyer bankruptcy shield: this sale conveys artifacts, not IP; a Buyer bankruptcy has nothing to convey to the trustee beyond the physical + digital artifacts already delivered. The inventor's IP is not part of the estate and cannot be reassigned. Seller has not filed for bankruptcy.
- Included capabilities in the All-In-One bundle at no additional charge; this SKU exists for buyers who want everything from this specific session as a discrete deliverable rather than the full 59-project portfolio.
Estimated ceiling and upgrade path (formal statement)
In addition to every other statement in this listing, the following performance envelope is formally disclosed to prospective buyers:
- Design size: approximately 10 million transistors per design before pure-Python
solve()becomes uncomfortable on typical hardware. - Format: the
.wpprog v2byte-stream format can address approximately 4 billion nets per design (32-bit net IDs). The bottleneck at large scale is the pure-Python solver, not the format. - C-inner-loop upgrade (~1 day of engineering work): approximately 50-100x faster solve throughput on the same designs.
- CUDA upgrade (~1 week of engineering work): approximately 1,000-10,000x faster solve throughput, sufficient to simulate 11 million-FET designs in seconds.
These are honest projections based on the current pure-Python implementation. Neither the C inner loop nor the CUDA kernel ships in the current release. Buyer is welcome to implement either upgrade under the terms of the No IP Conveyed clause (personal / internal research use only; no commercial exploitation without separate written agreement with the inventor).
